? semiconductor components industries, llc, 2015 september, 2015 ? rev. 2 1 publication order number: NCV894530/d NCV894530 1.2 a - 2.1 mhz high efficiency low voltage step-down converter the NCV894530 step?down dc?dc converter is a monolithic integrated circuit dedicated to automotive driver information systems from a downstream voltage rail. the output voltage is externally adjustable from 0.9 v to 3.3 v and can source up to 1.2 a. the converter is running at a 2.1 mhz switching frequency, above the sensitive am band. the NCV894530 provides additional features expected in automotive power systems such as integrated soft?start, hiccup mode current limit and thermal shutdown protection. the device can also be synchronized to an external clock signal in the range of 2.1 mhz. the NCV894530 is available in the same 3x3 mm 10?pin dfn package as the dual ncv896530, with compatible pin?out. features ? synchronous rectification for higher efficiency ? 2.1 mhz switching frequency ? sources up to 1.2 a ? adjustable output voltage from 0.9 v to 3.3 v ? 2.7 v to 5.5 v input voltage range ? thermal limit and short circuit protection ? auto synchronizes with an external clock ? wettable flanks ? dfn ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free and are rohs compliant typical applications ? audio ? infotainment ? safety ? v ision system ? instrumentation www.onsemi.com marking diagram device package shipping ? ordering information dfn10 case 485c NCV894530mwtxg dfn10 (pb?free) 3000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. ncv89 4530 = specific device code a = assembly location l = wafer lot y = year w = work week = pb?free package pin connections ncv89 4530 al y w . . (note: microdot may be in either location) fb 1 en 2 sync 3 vin 4 sw 5 10 gnd 9 nc 8 por 7 gnd 6 nc (top view)
NCV894530 www.onsemi.com 2 figure 1. NCV894530 typical application v in v in c in l sw v out c out v dd NCV894530 c 1 r 1 microprocessor 1.8 ? 2.7 mhz off on sync en fb por v in or v out r 2 r por reset gnd 2.2 h 20 f 10 f block diagram figure 2. simplified block diagram uvlo current limit v in en enable softstart por thermal shutdown reference logic and sw pwm latch ea fb sync slope compensaton oscillator gnd pin function description pin pin name type description 1 fb analog input feedback voltage. this is the input to the error amplifier. 2 en digital input enable. this pin is active high (equal or lower analog input voltage) and is turned off by logic low. do not let this pin float. 3 sync digital input oscillator synchronization. this pin can be synchronized to an external clock in the range of 2.1 mhz. if not used, the pin must be connected to ground. 4 vin analog / power input power supply input for the pfet power stage, analog and digital blocks. the pin must be decoupled to ground by a 10 f ceramic capacitor. 5 sw power output connection from power mosfets of output to the inductor.
NCV894530 www.onsemi.com 3 pin function description pin description type pin name 6 nc ? 7 gnd analog / power ground this pin is the ground reference for the analog section of the ic. the pin must be connected to the system ground. both pins must be connected together on pcb. 8 por digital output power on reset. this is an open drain output. this output is shutting down when the output voltage is less than 90% (typ) of their nominal values. an external pull?up resistor should be connected between por and v in or v out depending on the supplied device. 9 nc ? 10 gnd analog ground connect this pin to ground. epad epad exposed pad connected to gnd potential. absolute maximum ratings (refer to electrical characteristics and application information for safe operating area.) rating symbol min max unit input voltage v in ?0.3 6.0 v sw voltage v sw ?0.3 6 v (or v in + 0.3 v)* v enable input voltage v en ?0.3 6 v (or v in + 0.3 v)* v feedback input voltage v fb ?0.3 6 v (or v in + 0.3 v)* v oscillator synchronization input voltage v sync ?0.3 6 v (or v in + 0.3 v)* v power on reset voltage v por ?0.3 6 v (or v in + 0.3 v)* v junction temperature t j ?40 150 c storage temperature t stg ?55 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. *whichever is lower. esd capability (note 1) rating symbol min max unit esd capability, human body model esdhbm ?2 2 kv esd capability, machine model esdmm ?200 200 v 1. this device series incorporates esd portection and is tested by the following methods: esd human body model tested per aec?q100?002 (js?001?2010) esd machine model tested per aec?q100?003 (eia/jesd22?a115) lead soldering temperature and msl (note 2) rating symbol min max unit moisture sensitivity level msl 3 per ipc lead temperature soldering reflow (smd styles only), pb?free versions t sld 265 peak c 2. for more information, please refer to our soldering and mounting techniques reference manual, solderrm/d. thermal characteristics rating symbol value unit thermal characteristics, dfn10 (note 3) thermal resistance, junction?to?air r ja 40 c/w 3. values based on copper area of 645 mm 2 (or 1 in 2 ) of 1 oz copper thickness and fr4 pcb substrate.
NCV894530 www.onsemi.com 4 electrical characteristics (2.7 v < v in < 5.5 v, min and max values are valid for the temperature range ?40 c t j +150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. typical values are referenced to t a = +25 c) rating conditions symbol min typ max unit input voltage quiescent current sync = gnd, v fb = 0 v, en = 2 v, (no switching) i q ? 1.0 2.0 ma shutdown current en = 0 v i off ? ? 10 a under voltage lockout v in falling v uvlo 2.2 2.4 2.6 v under voltage hysteresis v uvloh ? 100 150 mv sync sync threshold voltage logic low logic high v ilsync v ihsync ? 1.2 ? ? 0.4 ? v sync input current v sync = 5 v i sync 2.0 ? 50 a external synchronization f sync 1.8 ? 2.7 mhz sync pulse duty ratio d sync ? 50 ? % enable enable threshold voltage logic low logic high v ilen v ihen ? 1.2 ? ? 0.4 ? v enable input current v en = 5 v i en 2 ? 50 a power on reset power on reset threshold v out falling v port 87 90 93 %vout power on reset hysteresis v porh ? ? 3.0 %vout por sink current v por = 0.4 v i por 2.0 ? ? ma feedback voltage feedback voltage (accuracy %) t j = ?40 c to 125 c v fb 0.591 (?1.5%) 0.6 0.609 (+1.5%) v soft?start time time from en to 90% of v fb t ss 1700 ? 3200 s switching frequency switching frequency f sw 1.8 2.1 2.4 mhz duty cycle d ? ? 100 % minimum on time t onmin ? ? 80 ns power switches high?side mosfet on?resistance i rds(on) = 0.6 a, v in = 5 v, t j = 25 c r ds(on)h ? 500 820 m low?side mosfet on?resistance i rds(on) = 0.6 a, v in = 5 v, t j = 25 c r ds(on)l ? 450 820 m high?side mosfet leakage current v in = 5 v, v sw = 0 v, v en = 0 v i ds(off)h ? ? 5.0 a low?side mosfet leakage current v sw = 5 v, v en = 0 v i ds(off)l ? ? 5.0 a current limit protection current limit peak inductor current (100% duty cycle) i pk 1.9 ? 2.5 a thermal shutdown thermal shutdown temperature guaranteed by design t sd 150 170 190 c thermal shutdown hysteresis guaranteed by design t sh 5.0 ? 20 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
NCV894530 www.onsemi.com 5 typical characteristics curves v in , input voltage (v) f sw , switching frequency (mhz) figure 3. switching frequency vs. input voltage v sync , sync voltage (v) i sync , sync pulldown current ( a) figure 4. sync pulldown current vs. sync voltage v en , enable voltage (v) i en , enable pulldown current ( a) figure 5. enable pulldown current vs. enable voltage v in , input voltage (v) i stbmax , standby current ( a) figure 6. standby current vs. input voltage t j , junction temperature ( c) i pk , current limit (a) figure 7. current limit vs. temperature v ref , reference voltage (mv) t j , junction temperature ( c) figure 8. reference voltage vs. temperature 2.30 2.25 2.15 2.05 2.00 2.5 5.5 5.0 4.5 3.0 3.5 4.0 12 0 5.0 4.5 1.0 0.5 3.5 4.0 10 8 6 4 2 0 3.0 1.5 2.0 2.5 12 05 4 3 10 8 6 4 2 0 2 1 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 5.5 5.0 4.5 4.0 3.5 3.0 2.20 ?40 110 60 10 2.15 2.10 2.05 2.00 600.0 ?40 110 60 10 599.6 599.2 598.8 598.4 598.0 t j = 25 c en1 = 1 2.10 2.20 t j = 25 c t j = 25 c t j = 25 c 160 160
NCV894530 www.onsemi.com 6 typical characteristics curves t j , junction temperature ( c) i en , enable pulldown current ( a) figure 9. enable pulldown current vs. temperature t j , junction temperature ( c) i sync , sync pulldown current ( a) figure 10. sync pulldown current vs. temperature t j , junction temperature ( c) f sw , switching frequency (mhz) figure 11. switching frequency vs. temperature 12.0 ?40 160 110 10 12 10 8 6 4 2 0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 60 160 110 60 ?40 10 14 2.25 2.20 2.15 2.10 2.05 ?40 10 60 110 v en = 5 v v sync = 5 v v in = 5 v en1 = 1 160
NCV894530 www.onsemi.com 7 application information pwm operating mode the output voltage of the device is regulated by modulating the on?time pulse width of the main switch pmos at a fixed 2.1 mhz frequency (figure 2). the switching of the pmos is controlled by a flip?flop driven by the internal oscillator and a comparator that compares the error signal from an error amplifier with the sum of the sensed current signal and compensation ramp. the driver switches on and off the upper side transistor and switches the lower side transistor in either on state or in current source mode. at the beginning of each cycle, the main switch is turned on by the rising edge of the internal oscillator clock. the inductor current ramps up until the sum of the current sense signal and compensation ramp becomes higher than the error amplifier?s voltage. once this has occurred, the pwm comparator resets the flip?flop, pmos is turned off while the synchronous switch nmos is turned in its current source mode. nmos replaces the external schottky diode to reduce the conduction loss and improve the efficiency. to avoid overall power loss, a certain amount of dead time is introduced to ensure pmos is completely turned off before nmos is being turned on. soft?start the NCV894530 uses soft start to limit the inrush current when the device is initially powered up or enabled. soft?start is implemented by gradually increasing the reference voltage until it reaches the full reference voltage. during startup, a pulsed current source charges the internal soft?start capacitor to provide gradually increasing reference voltage. when the voltage across the capacitor ramps up to the nominal reference voltage, the pulsed current source will be switched off and the reference voltage will switch to the regular reference voltage. over current hiccup protection when the current through the inductor exceeds the current limit the NCV894530 enters over current hiccup mode. when an over current event is detected the NCV894530 disables the outputs and attempts to re?enable the outputs after the hiccup time. the part remains off for the hiccup time and then goes through the power on reset procedure. if the excessive load has been removed then the output stage re?enables and operates normally; however, if the exce ssive load is still present the cycle begins again. internal heat dissipation is kept to a minimum as current will only flow during the reset time of the protection circuitry. the hiccup mode is continuous until the excessive load is removed. the hiccup current limit in switching mode is 300 ma lower than it in low dropout mode (100% duty cycle). low dropout operation the NCV894530 offers a low input?to?output voltage difference. the NCV894530 can operate at 100% duty cycle. in this mode the pmos remains completely on. the minimum input voltage to maintain regulation can be calculated as: v in(min) v out(max) i out r ds(on) r inductor (eq. 1) v out : output voltage i out : max output current r ds(on) : p=channel switch r ds(on) r inductor : inductor resistance (dcr) power on reset the power on reset (por) is pulled low when the converter is out of 90% of the regulation. when output is in the range of regulation, a pull up resistor is needed to this open drain output. this resistor may be connected to vin or vout if the device supplied cannot accept vin on the io pins. por is low when NCV894530 is off. leave the por pin unconnected when not used. frequency synchronization the NCV894530 can be synchronized with an external clock signal by the sync pin (1.8 mhz ? 2.7 mhz). thermal shutdown internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. if the junction temperature exceeds tsd, the device shuts down. in this mode all power transistors and control circuits are turned off. the device restarts in soft?start after the temperature drops below 130 c min. this feature is provided to prevent catastrophic failures from accidental device overheating.
NCV894530 www.onsemi.com 8 package dimensions dfn10, 3x3, 0.5p case 485c issue c 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. 7. for device opn containing w option, detail b alternate construction is not applicable. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCV894530/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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